Advanced transistors with punch through suppression

ABSTRACT

An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10 18  dopant atoms per cm 3 . At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.12/895,813 filed Sep. 30, 2010 claiming the benefit of U.S. ProvisionalApplication No. 61/247,300 filed Sep. 30, 2009, U.S. ProvisionalApplication No. 61/262,122 filed Nov. 17, 2009, U.S. application Ser.No. 12/708,497 filed Feb. 18, 2010, and U.S. Provisional Application No.61/357,492 filed Jun. 22, 2010, the disclosure of each beingincorporated by reference herein.

TECHNICAL FIELD OF THE INVENTION

This disclosure relates to structures and processes for forming advancedtransistors with improved operational characteristics, includingenhanced punch through suppression.

BACKGROUND OF THE INVENTION

Fitting more transistors onto a single die is desirable to reduce costof electronics and improve their functional capability. A commonstrategy employed by semiconductor manufacturers is to simply reducegate size of a field effect transistor (FET), and proportionally shrinkarea of the transistor source, drain, and required interconnects betweentransistors. However, a simple proportional shrink is not alwayspossible because of what are known as “short channel effects”. Shortchannel effects are particularly acute when channel length under atransistor gate is comparable in magnitude to depletion depth of anoperating transistor, and include reduction in threshold voltage, severesurface scattering, drain induced barrier lowering (DIBL), source-drainpunch through, and electron mobility issues.

Conventional solutions to mitigate some short channel effects caninvolve implantation of pocket or halo implants around the source andthe drain. Halo implants can be symmetrical or asymmetrical with respectto a transistor source and drain, and typically provide a smootherdopant gradient between a transistor well and the source and drains.Unfortunately, while such implants improve some electricalcharacteristics such as threshold voltage rolloff and drain inducedbarrier lowering, the resultant increased channel doping adverselyaffects electron mobility, primarily because of the increased dopantscattering in the channel.

Many semiconductor manufacturers have attempted to reduce short channeleffects by employing new transistor types, including fully or partiallydepleted silicon on insulator (SOI) transistors. SOI transistors arebuilt on a thin layer of silicon that overlies an insulator layer, havean undoped or low doped channel that minimizes short channel effects,and do not require either deep well implants or halo implants foroperation. Unfortunately, creating a suitable insulator layer isexpensive and difficult to accomplish. Early SOI devices were built oninsulative sapphire wafers instead of silicon wafers, and are typicallyonly used in specialty applications (e.g. military avionics orsatellite) because of the high costs. Modem SOI technology can usesilicon wafers, but require expensive and time consuming additionalwafer processing steps to make an insulative silicon oxide layer thatextends across the entire wafer below a surface layer of device-qualitysingle-crystal silicon.

One common approach to making such a silicon oxide layer on a siliconwafer requires high dose ion implantation of oxygen and high temperatureannealing to form a buried oxide (BOX) layer in a bulk silicon wafer.Alternatively, SOI wafers can be fabricated by bonding a silicon waferto another silicon wafer (a “handle” wafer) that has an oxide layer onits surface. The pair of wafers are split apart, using a process thatleaves a thin transistor quality layer of single crystal silicon on topof the BOX layer on the handle wafer. This is called the “layertransfer” technique, because it transfers a thin layer of silicon onto athermally grown oxide layer of the handle wafer.

As would be expected, both BOX formation or layer transfer are costlymanufacturing techniques with a relatively high failure rate.Accordingly, manufacture of SOI transistors not an economicallyattractive solution for many leading manufacturers. When cost oftransistor redesign to cope with “floating body” effects, the need todevelop new SOI specific transistor processes, and other circuit changesis added to SOI wafer costs, it is clear that other solutions areneeded.

Another possible advanced transistor that has been investigated usesmultiple gate transistors that, like SOI transistors, minimize shortchannel effects by having little or no doping in the channel. Commonlyknown as a finFET (due to a fin-like shaped channel partially surroundedby gates), use of finFET transistors has been proposed for transistorshaving 28 nanometer or lower transistor gate size. But again, like SOItransistors, while moving to a radically new transistor architecturesolves some short channel effect issues, it creates others, requiringeven more significant transistor layout redesign than SOI. Consideringthe likely need for complex non-planar transistor manufacturingtechniques to make a finFET, and the unknown difficulty in creating anew process flow for finFET, manufacturers have been reluctant to investin semiconductor fabrication facilities capable of making finFETs.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of embodiments of the invention will beapparent from the detailed description taken in conjunction with theaccompanying drawings wherein like reference numerals represent likeparts, in which:

FIG. 1 illustrates a DDC transistor with a punch through suppression;

FIG. 2 illustrates a dopant profile of a DDC transistor with enhancedpunch through suppression;

FIGS. 3-7 illustrate alternative useful dopant profiles; and

FIG. 8 is a flow diagram illustrating one exemplary process for forminga DDC transistor with a punch through suppression.

DETAILED DESCRIPTION OF THE INVENTION

Unlike silicon on insulator (SOI) transistors, nanoscale bulk CMOStransistors (those typically having a gate length less than 100nanometers) are subject to significant adverse short channel effects,including body leakage through both drain induced barrier lowering(DIBL) and source drain punch through. Punch through is associated withthe merging of source and drain depletion layers, causing the draindepletion layer to extend across a doped substrate and reach the sourcedepletion layer, creating a conduction path or leakage current betweenthe source and drain. This results in a substantial increase in requiredtransistor electrical power, along with a consequent increase intransistor heat output and decrease in operational lifetime for portableor battery powered devices using such transistors.

An improved transistor manufacturable on bulk CMOS substrates is seen inFIG. 1. A Field Effect Transistor (FET) 100 is configured to havegreatly reduced short channel effects, along with enhanced punch throughsuppression according to certain described embodiments. The FET 100includes a gate electrode 102, source 104, drain 106, and a gatedielectric 108 positioned over a channel 110. In operation, the channel110 is deeply depleted, forming what can be described as deeply depletedchannel (DDC) as compared to conventional transistors, with depletiondepth set in part by a highly doped screening region 112. While thechannel 110 is substantially undoped, and positioned as illustratedabove a highly doped screening region 112, it may include simple orcomplex layering with different dopant concentrations. This dopedlayering can include a threshold voltage set region 111 with a dopantconcentration less than screening region 112, optionally positionedbetween the gate dielectric 108 and the screening region 112 in thechannel 110. A threshold voltage set region 111 permits smalladjustments in operational threshold voltage of the FET 100, whileleaving the bulk of the channel 110 substantially undoped. Inparticular, that portion of the channel 110 adjacent to the gatedielectric 108 should remain undoped. Additionally, a punch throughsuppression region 113 is formed beneath the screening region 112. Likethe threshold voltage set region 111, the punch through suppressionregion 113 has a dopant concentration less than screening region 112,while being higher than the overall dopant concentration of a lightlydoped well substrate 114.

In operation, a bias voltage 122 VBS may be applied to source 104 tofurther modify operational threshold voltage, and P+ terminal 126 can beconnected to P-well 114 at connection 124 to close the circuit. The gatestack includes a gate electrode 102, gate contact 118 and a gatedielectric 108. Gate spacers 130 are included to separate the gate fromthe source and drain, and optional Source/Drain Extensions (SDE) 132, or“tips” extend the source and drain under the gate spacers and gatedielectric 108, somewhat reducing the gate length and improvingelectrical characteristics of FET 100.

In this exemplary embodiment, the FET 100 is shown as an N-channeltransistor having a source and drain made of N-type dopant material,formed upon a substrate as P-type doped silicon substrate providing aP-well 114 formed on a substrate 116. However, it will be understoodthat, with appropriate change to substrate or dopant material, anonsilicon P-type semiconductor transistor formed from other suitablesubstrates such as Gallium Arsenide based materials may be substituted.The source 104 and drain 106 can be formed using conventional dopantimplant processes and materials, and may include, for example,modifications such as stress inducing source/drain structures, raisedand/or recessed source/drains, asymmetrically doped, counter-doped orcrystal structure modified source/drains, or implant doping ofsource/drain extension regions according to LDD (low doped drain)techniques. Various other techniques to modify source/drain operationalcharacteristics can also be used, including, in certain embodiments, useof heterogeneous dopant materials as compensation dopants to modifyelectrical characteristics.

The gate electrode 102 can be formed from conventional materials,preferably including, but not limited to, metals, metal alloys, metalnitrides and metal silicides, as well as laminates thereof andcomposites thereof. In certain embodiments the gate electrode 102 mayalso be formed from polysilicon, including, for example, highly dopedpolysilicon and polysilicon-germanium alloy. Metals or metal alloys mayinclude those containing aluminum, titanium, tantalum, or nitridesthereof, including titanium containing compounds such as titaniumnitride. Formation of the gate electrode 102 can include silicidemethods, chemical vapor deposition methods and physical vapor depositionmethods, such as, but not limited to, evaporative methods and sputteringmethods. Typically, the gate electrode 102 has an overall thickness fromabout 1 to about 500 nanometers.

The gate dielectric 108 may include conventional dielectric materialssuch as oxides, nitrides and oxynitrides. Alternatively, the gatedielectric 108 may include generally higher dielectric constantdielectric materials including, but not limited to hafnium oxides,hafnium silicates, zirconium oxides, lanthanum oxides, titanium oxides,barium-strontium-titanates and lead-zirconate-titanates, metal baseddielectric materials, and other materials having dielectric properties.Preferred hafnium-containing oxides include HfO₂, HfZrO_(x), HfSiO_(x),HfTiO_(x), HfAlO_(x), and the like. Depending on composition andavailable deposition processing equipment, the gate dielectric 108 maybe formed by such methods as thermal or plasma oxidation, nitridationmethods, chemical vapor deposition methods (including atomic layerdeposition methods) and physical vapor deposition methods. In someembodiments, multiple or composite layers, laminates, and compositionalmixtures of dielectric materials can be used. For example, a gatedielectric can be formed from a SiO₂-based insulator having a thicknessbetween about 0.3 and 1 nm and the hafnium oxide based insulator havinga thickness between 0.5 and 4 nm. Typically, the gate dielectric has anoverall thickness from about 0.5 to about 5 nanometers.

The channel region 110 is formed below the gate dielectric 108 and abovethe highly doped screening region 112. The channel region 110 alsocontacts and extends between, the source 104 and the drain 106.Preferably, the channel region includes substantially undoped siliconhaving a dopant concentration less than 5×10¹⁷ dopant atoms per cm³adjacent or near the gate dielectric 108. Channel thickness cantypically range from 5 to 50 nanometers. In certain embodiments thechannel region 110 is formed by epitaxial growth of pure orsubstantially pure silicon on the screening region.

As disclosed, the threshold voltage set region 111 is positioned underthe gate dielectric 108, spaced therefrom, and above screening region112, and is typically formed as a thin doped layer. Suitably varyingdopant concentration, thickness, and separation from the gate dielectricand the screening region allows for controlled slight adjustments ofthreshold voltage in the operating FET 100. In certain embodiments, thethreshold voltage set region 111 is doped to have a concentrationbetween about 1×10¹⁸ dopant atoms per cm3 and about 1×10¹⁹ dopant atomsper cm³. The threshold voltage set region 111 can be formed by severaldifferent processes, including 1) in-situ epitaxial doping, 2) epitaxialgrowth of a thin layer of silicon followed by a tightly controlleddopant implant, 3) epitaxial growth of a thin layer of silicon followedby dopant diffusion of atoms from the screening region 112, or 4) by anycombination of these processes (e.g. epitaxial growth of siliconfollowed by both dopant implant and diffusion from the screening layer112).

Position of a highly doped screening region 112 typically sets depth ofthe depletion zone of an operating FET 100. Advantageously, thescreening region 112 (and associated depletion depth) are set at a depththat ranges from one comparable to the gate length (Lg/l) to a depththat is a large fraction of the gate length (Lg/5). In preferredembodiments, the typical range is between Lg/3 to Lg/1.5. Devices havingan Lg/2 or greater are preferred for extremely low power operation,while digital or analog devices operating at higher voltages can oftenbe formed with a screening region between Lg/5 and Lg/2. For example, atransistor having a gate length of 32 nanometers could be formed to havea screening region that has a peak dopant density at a depth below thegate dielectric of about 16 nanometers (Lg/2), along with a thresholdvoltage set region at peak dopant density at a depth of 8 nanometers(Lg/4).

In certain embodiments, the screening region 112 is doped to have aconcentration between about 5×10¹⁸ dopant atoms per cm³ and about 1×10²⁰dopant atoms per cm³, significantly more than the dopant concentrationof the undoped channel, and at least slightly greater than the dopantconcentration of the optional threshold voltage set region 111. As willbe appreciated, exact dopant concentrations and screening region depthscan be modified to improve desired operating characteristics of FET 100,or to take in to account available transistor manufacturing processesand process conditions.

To help control leakage, the punch through suppression region 113 isformed beneath the screening region 112. Typically, the punch throughsuppression region 113 is formed by direct implant into a lightly dopedwell, but it may be formed by out-diffusion from the screening region,in-situ growth, or other known process. Like the threshold voltage setregion 111, the punch through suppression region 113 has a dopantconcentration less than the screening region 112, typically set betweenabout 1×10¹⁸ dopant atoms per cm³ and about 1×10¹⁹ dopant atoms per cm³.In addition, the punch through suppression region 113 dopantconcentration is set higher than the overall dopant concentration of thewell substrate. As will be appreciated, exact dopant concentrations anddepths can be modified to improve desired operating characteristics ofFET 100, or to take in to account available transistor manufacturingprocesses and process conditions.

Forming such a FET 100 is relatively simple compared to SOI or finFETtransistors, since well developed and long used planar CMOS processingtechniques can be readily adapted.

Together, the structures and the methods of making the structures allowfor FET transistors having both a low operating voltage and a lowthreshold voltage as compared to conventional nanoscale devices.Furthermore, DDC transistors can be configured to allow for thethreshold voltage to be statically set with the aid of a voltage bodybias generator. In some embodiments the threshold voltage can even bedynamically controlled, allowing the transistor leakage currents to begreatly reduced (by setting the voltage bias to upwardly adjust theV_(T) for low leakage, low speed operation), or increased (by downwardlyadjusting the V_(T) for high leakage, high speed operation). Ultimately,these structures and the methods of making structures provide fordesigning integrated circuits having FET devices that can be dynamicallyadjusted while the circuit is in operation. Thus, transistors in anintegrated circuit can be designed with nominally identical structure,and can be controlled, modulated or programmed to operate at differentoperating voltages in response to different bias voltages, or to operatein different operating modes in response to different bias voltages andoperating voltages. In addition, these can be configuredpost-fabrication for different applications within a circuit.

As will be appreciated, concentrations of atoms implanted or otherwisepresent in a substrate or crystalline layers of a semiconductor tomodify physical and electrical characteristics of a semiconductor are bedescribed in terms of physical and functional regions or layers. Thesemay be understood by those skilled in the art as three-dimensionalmasses of material that have particular averages of concentrations. Or,they may be understood as sub-regions or sub-layers with different orspatially varying concentrations. They may also exist as small groups ofdopant atoms, regions of substantially similar dopant atoms or the like,or other physical embodiments. Descriptions of the regions based onthese properties are not intended to limit the shape, exact location ororientation. They are also not intended to limit these regions or layersto any particular type or number of process steps, type or numbers oflayers (e.g., composite or unitary), semiconductor deposition, etchtechniques, or growth techniques utilized. These processes may includeepitaxially formed regions or atomic layer deposition, dopant implantmethodologies or particular vertical or lateral dopant profiles,including linear, monotonically increasing, retrograde, or othersuitable spatially varying dopant concentration. To ensure that desireddopant concentrations are maintained, various dopant anti-migrationtechniques, are contemplated, including low temperature processing,carbon doping, in-situ dopant deposition, and advanced flash or otherannealing techniques. The resultant dopant profile may have one or moreregions or layers with different dopant concentrations, and thevariations in concentrations and how the regions or layers are defined,regardless of process, mayor may not be detectable via techniquesincluding infrared spectroscopy, Rutherford Back Scattering (RBS),Secondary Ion Mass Spectroscopy (SIMS), or other dopant analysis toolsusing different qualitative or quantitative dopant concentrationdetermination methodologies.

To better appreciate one possible transistor structure, FIG. 2illustrates a dopant profile 202 of a deeply depleted transistor takenat midline between a source and drain, and extending downward from agate dielectric toward a well. Concentration is measured in number ofdopant atoms per cubic centimeter, and downward depth is measured as aratio of gate length Lg. Measuring as a ratio rather than absolute depthin nanometers better allows cross comparison between transistorsmanufactured at different nodes (e.g. 45 nm, 32 nm, 22 nm, or 15 nm)where nodes are commonly defined in term of minimum gate lengths.

As seen in FIG. 2, the region of the channel 210 adjacent to the gatedielectric is substantially free of dopants, having less than 5×10¹⁷dopant atoms per cm³ to a depth of nearly Lg/4. A threshold voltage setregion 211 increases the dopant concentration to about 3×10¹⁸ dopantatoms per cm³, and the concentration increases another order ofmagnitude above 3×10¹⁸ dopant atoms per cm³ to form the screening region212 that sets the base of the depletion zone in an operating transistor.A punch through suppression region 213 having a dopant concentration ofabout 1×10¹⁹ dopant atoms per cm³ at a depth of about Lg/1 isintermediate between the screening region and the lightly doped well214. Without the punch through suppression region, a transistorconstructed to have, for example, a 30 nm gate length and an operatingvoltage of 1.0 volts would be expected to have significantly greaterleakage. When the disclosed punch through suppression region isimplanted, punch through leakage is reduced, making the transistor morepower efficient, and better able to tolerate process variations intransistor structure without punch through failure.

This is better seen with respect to the following Table 1, whichindicates expected performance improvements for a range of punch throughdosage and threshold voltage:

TABLE 1 Ioff (nA/um) Idsat (mA/um) Vt (V) Target Punchthrough layer 20.89 0.31 No Punchthrough layer 70 1 0.199 Higher Dose Punchthrough 0.90.54 0.488 Very deep Punchthrough 15 1 0.237

Alternative dopant profiles are contemplated. As seen in FIG. 3, analternative dopant profile 203 that includes a slightly increased depthfor the low doped channel is shown. In contrast to the embodiments ofFIG. 2, the threshold voltage set region 211 is a shallow notchprimarily formed by out-diffusion into an epitaxially deposited layer ofsilicon from the screening region 212. The screening region 212 itselfis set to have a dopant concentration greater than 3×10¹⁸ dopant atomsper cm³. The punch through suppression region 213 has a dopantconcentration of about 8×10¹⁸ dopant atoms per cm³, provided by acombination of out-diffusion from the screening region 212 and aseparate low energy implant.

As seen in FIG. 4, an alternative dopant profile 204 that includes agreatly increased depth for the low doped channel is shown. In contrastto the embodiments of FIGS. 2 and 3, there is no distinct notch, planeor layer to aid in threshold voltage setting. The screening region 212is set to be greater than 3×10¹⁹ dopant atoms per cm³ and the punchthrough suppression region 213 has a similarly high, yet narrowlydefined dopant concentration of about 8×10¹⁸ dopant atoms per cm³,provided by with a separate low energy implant.

Yet another variation in dopant profile is seen in FIG. 5, whichillustrates a transistor dopant profile 205 for a transistor structurethat includes a very low doped channel 210. The threshold voltage setregion 211 is precisely formed by in-situ or well controlled implantdoping of thin epitaxial layer grown on the screening region. Thescreening region 212 is set to be about 1×10¹⁹ dopant atoms per cm³ andthe punch through suppression region 213 also has narrowly defineddopant concentration of about 8×10¹⁸ dopant atoms per cm³, provided bywith a separate low energy implant. The well implant 214 concentrationis gradually reduced to about 5×10¹⁷ dopant atoms per cm³.

As seen in FIG. 6, a dopant profile 206 includes a low doped channel 210adjacent to the gate dielectric, and a narrowly defined thresholdvoltage set region 211. The screening region 212 increases to a narrowpeak set to be about 1×10¹⁹ dopant atoms per cm³ and the punch throughsuppression region 213 also has broadly peak dopant concentration ofabout 5×10¹⁸ dopant atoms per cm³, provided by with a separate lowenergy implant. The well implant 214 concentration is high to improvebias coefficient of the transistor, with a concentration of about 8×10¹⁷dopant atoms per cm³.

In contrast to the narrow screen region peak dopant concentration ofFIG. 6, the dopant profile 207 of FIG. 7 has a broad peak 212. Inaddition to a narrow undoped channel 210, the transistor structureincludes a well defined partially retrograde threshold set 211, and adistinct separate punch through suppression peak 213. The well 214doping concentration is relatively low, less than about 5×10¹⁷ dopantatoms per cm³.

FIG. 8 is a schematic process flow diagram 300 illustrating oneexemplary process for forming a transistor with a punch throughsuppression region and a screening region suitable for different typesof FET structures, including both analog and digital transistors. Theprocess illustrated here is intended to be general and broad in itsdescription in order not to obscure the inventive concepts, and moredetailed embodiments and examples are set forth below. These along withother process steps allow -for the processing and manufacture ofintegrated circuits that include DDC structured devices together withlegacy devices, allowing for designs to cover a full range of analog anddigital devices with improved performance and lower power.

In Step 302, the process begins at the well formation, which may be oneof many different processes according to different embodiments andexamples. As indicated in 303, the well formation may be before or afterSTI (shallow trench isolation) formation 304, depending on theapplication and results desired. Boron (B), indium (I) or other P-typematerials may be used for P-type implants, and arsenic (As) orphosphorous (P) and other N-type materials may be used for N-typeimplants. For the PMOS well implants, the P+ implant may be implantedwithin a range from 10 to 80 keV, and at NMOS well implants, the boronimplant B+ implant may be within a range of 0.5 to 5 keV, and within aconcentration range of 1×10¹³ to 8×10¹³/cm². A germanium implant Ge+,may be performed within a range of 10 to 60 keV, and at a concentrationof 1×10¹⁴ to 5×10¹⁴/cm². To reduce dopant migration, a carbon implant,C+ may be performed at a range of 0.5 to 5 keV, and at a concentrationof 1×10¹³ to 8×10¹³/cm². Well implants may include sequential implant,and/or epitaxial growth and implant, of punch through suppressionregions, screen regions having a higher dopant density than the punchthrough suppression region, and threshold voltage set regions (whichpreviously discussed are typically formed by implant or diffusion ofdopants into a grown epitaxial layer on the screening region).

In some embodiments the well formation 302 may include a beam lineimplant of Ge/B (N), As (P), followed by an epitaxial (EPI) pre-cleanprocess, and followed finally non-selective blanket EPI deposition, asshown in 302A. Alternatively, the well may be formed using a plasmaimplant of B (N), As (P), followed by an EPI pre-clean, then finally anon-selective (blanket) EPI deposition, 302B. The well formation mayalternatively include a solid-source diffusion of B(N), As(P), followedby an EPI pre-clean, and followed finally by a non-selective (blanket)EPI deposition, 302C. The well formation may alternatively include asolid-source diffusion of B (N), As (P), followed by an EPI pre-clean,and followed finally by a non-selective (blanket) EPI deposition, 302D.As yet another alternative, well formation may simply include wellimplants, followed by in-situ doped selective EPI of B (N), P (P).Embodiments described herein allow for anyone of a number of devicesconfigured on a common substrate with different well structures andaccording to different parameters.

Shallow trench isolation (STI) formation 304, which, again, may occurbefore or after well formation 302, may include a low temperature trenchsacrificial oxide (TSOX) liner 304A at a temperature lower than 900° C.The gate stack 306 may be formed or otherwise constructed in a number ofdifferent ways, from different materials, and of different workfunctions. One option is a poly/SiON gate stack 306A. Another option isa gate-first process 306B that includes SiON/Metal/Poly and/orSiON/Poly, followed by High-K/Metal Gate. Another option, a gate-lastprocess 306C includes a high-K/metal gate stack wherein the gate stackcan either be formed with “Hi-K first-Metal gate last” flow or and “Hi-Klast-Metal gate last” flow. Yet another option, 306D is a metal gatethat includes a tunable range of work functions depending on the deviceconstruction, N(NMOS)/P(PMOS)N(PMOS)/P(NMOS)/Mid-gap or anywhere inbetween. In one example, N has a work function (WF) of 4.05 V±200 mV,and P has a WF of 5.01 V±200 mV.

Next, in Step 308, Source/Drain tips may be implanted, or optionally maynot be implanted depending on the application. The dimensions of thetips can be varied as required, and will depend in part on whether gatespacers (SPCR) are used. In one option, there may be no tip implant in308A. Next, in optional steps 310 and 312, PMOS or NMOS EPI layers maybe formed in the source and drain regions as performance enhancers forcreating strained channels. For gate-last gate stack options, in Step314, a Gate-last module is formed. This may be only for gate-lastprocesses 314A.

Die supporting multiple transistor types, including those with andwithout a punch through suppression, those having different thresholdvoltages, and with and without static or dynamic biasing arecontemplated. Systems on a chip (SoC), advanced microprocessors, radiofrequency, memory, and other die with one or more digital and analogtransistor configurations can be incorporated into a device using themethods described herein. According to the methods and processesdiscussed herein, a system having a variety of combinations of DDCand/or transistor devices and structures with or without punch throughsuppression can be produced on silicon using bulk CMOS. In differentembodiments, the die may be divided into one or more areas where dynamicbias structures, static bias structures or no-bias structures existseparately or in some combination. In a dynamic bias section, forexample, dynamically adjustable devices may exist along with high andlow V_(T) devices and possibly DDC logic devices.

While certain exemplary embodiments have been described and shown in theaccompanying drawings, it is to be understood that such embodiments aremerely illustrative of and not restrictive on the broad invention, andthat this invention not be limited to the specific constructions andarrangements shown and described, since various other modifications mayoccur to those ordinarily skilled in the art.

Accordingly, the specification and drawings are to be regarded in anillustrative rather than a restrictive sense.

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions, andalterations can be made therein without departing from the spirit andscope of the invention as defined by the appended claims.

What is claimed is:
 1. A field effect transistor structure, comprising:a substrate; a gate atop the substrate; a source; a drain; a pluralityof distinct doped regions in the substrate underlying the gate andextending between the source and the drain, the plurality of dopedregions defining a dopant profile for the transistor, the dopant profilehaving a peak dopant concentration at a first depth from the gate and anintermediate dopant concentration at a second depth from the gate, theintermediate dopant concentration establishing a first notch in thedopant profile; and an epitaxially grown substantially undoped channelunderlying the gate and overlying the plurality of doped regions.
 2. Thetransistor of claim 1, wherein the first depth is deeper below the gatethan the second depth.
 3. The transistor of claim 1, wherein the firstdepth is shallower below the gate than the second depth.
 4. Thetransistor of claim 1, wherein the first depth is approximately one halfof a length of the gate.
 5. The transistor of claim 1, wherein thedopant profile includes a second intermediate dopant concentration at athird depth from the gate, the second intermediate dopant concentrationestablishing a second notch in the dopant profile.
 6. The transistor ofclaim 1, wherein the first depth sets a depletion depth for thetransistor when a voltage is applied to the gate.
 7. The transistor ofclaim 1, wherein the dopant concentration at the second depth isassociated with a threshold voltage of the transistor.
 8. The transistorof claim 1, further comprising: a bias structure coupled to the source,the bias structure operable to modify an operational threshold voltageof the transistor.
 9. The transistor of claim 8, further comprising: afixed voltage source coupled to the bias structure to statically set thethreshold voltage of the transistor.
 10. The transistor of claim 8,further comprising: a variable voltage source coupled to the biasstructure to dynamically adjust the threshold voltage of the transistor.11. A die, comprising: a substrate; a plurality of field effecttransistor structures supported by the substrate each having a gate, asource, and a drain; wherein at least one of the transistors has aplurality of doped regions in the substrate underlying the gate andextending between the source and drain, the plurality of doped regionsdefining a dopant profile for the transistor, the dopant profile havinga peak dopant concentration at a first depth from the gate and anintermediate dopant concentration at a second depth from the gate, theintermediate dopant concentration establishing a first notch in thedopant profile; wherein each of the plurality of transistors include achannel commonly formed by an undoped blanket epitaxial growth.
 12. Thetransistor of claim 11, wherein the dopant profile includes a secondintermediate dopant concentration at a third depth from the gate, thesecond intermediate dopant concentration establishing a second notch inthe dopant profile.
 13. The transistor of claim 11, wherein the peakdopant concentration at the first depth sets a depletion depth for thetransistor.
 14. The transistor of claim 11, wherein the dopantconcentration at the second depth is associated with a threshold voltageof the transistor.
 15. The die of claim 11, further comprising: a biasstructure coupled to the source of at least one transistor, the biasstructure operable to modify an operational threshold voltage of thetransistor.
 16. The die of claim 15, further comprising: a fixed voltagesource coupled to the bias structure to statically set the thresholdvoltage of the transistor.
 17. The die of claim 15, further comprising:a variable voltage source coupled to the bias structure to dynamicallyadjust the threshold voltage of the transistor.
 18. The die of claim 15,wherein the plurality of transistors are separated into different biassections, a first bias section providing no threshold voltageadjustment, a second bias section operable to provide static thresholdvoltage adjustment, and a third bias section operable to provide dynamicthreshold voltage adjustment.
 19. The die of claim 18, wherein any ofthe bias sections includes transistors with different threshold voltageswith or without any adjustment.